On Jan 1, 5:34 pm, "[email protected]" <[email protected]> wrote: > I have designed a cell lib in jelib format in electric, How can I use > for the synthesis tool such as DC?
Zheyu, You can't use it directly. Synopsys has its own internal format for library. What you need to do is the following: 1. For each cell in your .jelib, figure out what is the logic function of the cell. 2. Then you need to create a .lib file which is a text file. If you have synopsys installed you can look at the common installation paths and search for such files. Look for lsi_10k.lib or something like that. I'll upload a sample std_vill.lib that you can browse through. This file basically contains a bunch of wire models, and parameters about a technology process (voltage, etc) and the units. For each cell you need to specify the pin information for that cell, the cell's logic function, area, capacitance, timing parameters. Once you have this done right, goto 3 3. Open up DC compiler shell. You need to use the "read_lib" command to read in the lib file. 4. Then use the "write_lib" command to write the file in Synopsys proprietary format. 5. Now use this cell library for technology mapping once you have done synthesis. The netlist generated by Synopsys can then be used with Electric's silicon compiler to do automatic placement/routing. You can also browse through these tutorials (look at Lab 4/Synopsys DC compiler tutorial) on how to do this: http://cmosedu.com/cmos1/electric/electric.htm (look at 8-bit MIPS processor). Hope this helps. pallav -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
