That is how SPICE wraps a line that is longer than 40 characters. Jan
-----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of war_of_justice Sent: Wednesday, March 10, 2010 8:43 PM To: Electric VLSI Editor Subject: Re: Enquiry on Layout issue Hi *** SPICE deck for cell core_cell2_sim{lay} from library *core_cell_(square_circuit) *** Created on Mon Mar 08, 2010 00:02:21 *** Last revised on Thu Mar 11, 2010 11:30:40 *** Written on Thu Mar 11, 2010 11:33:07 by Electric VLSI Design System, *version 8.11 *** Layout tech: mocmos, foundry MOSIS *** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF .OPTIONS NOMOD NOPAGE *** SUBCIRCUIT core__cell2 FROM CELL core__cell2{lay} .SUBCKT core__cell2 Out b gnd in+ in- vdd Mnmos1 n...@270 in+ n...@4 gnd NMOS L=0.6U W=3U AS=9.9P AD=1.688P PS=15.3U +PD=4.65U Mnmos1a n...@34 in- n...@272 gnd NMOS L=0.6U W=3U AS=1.688P AD=9.9P PS=4.65U +PD=15.3U Mnmos2 n...@5 n...@4 vdd gnd NMOS L=0.6U W=3U AS=13.5P AD=2.7P PS=17.4U PD=4.8U Mnmos2a vdd n...@34 n...@8 gnd NMOS L=0.6U W=3U AS=2.7P AD=13.5P PS=4.8U +PD=17.4U Mnmos3 gnd n...@5 n...@5 gnd NMOS L=0.6U W=3U AS=2.7P AD=7.95P PS=4.8U PD=12.3U Mnmos3a n...@8 n...@8 gnd gnd NMOS L=0.6U W=3U AS=7.95P AD=2.7P PS=12.3U +PD=4.8U Mnmos4 gnd n...@5 n...@270 gnd NMOS L=0.6U W=3U AS=1.688P AD=7.95P PS=4.65U +PD=12.3U Mnmos4a n...@272 n...@8 gnd gnd NMOS L=0.6U W=3U AS=7.95P AD=1.688P PS=12.3U +PD=4.65U Mnmos6 Out n...@5 gnd gnd NMOS L=0.6U W=3U AS=7.95P AD=11.25P PS=12.3U +PD=15.6U Mnmos6a gnd n...@8 n...@32 gnd NMOS L=0.6U W=3U AS=11.25P AD=7.95P PS=15.6U +PD=12.3U Mpmos5 vdd b n...@4 vdd PMOS L=0.6U W=9U AS=9.9P AD=13.5P PS=15.3U PD=17.4U Mpmos5a n...@34 b vdd vdd PMOS L=0.6U W=9U AS=13.5P AD=9.9P PS=17.4U PD=15.3U Mpmos7 Out n...@32 vdd vdd PMOS L=0.6U W=9U AS=13.5P AD=11.25P PS=17.4U +PD=15.6U Mpmos7a vdd n...@32 n...@32 vdd PMOS L=0.6U W=9U AS=11.25P AD=13.5P PS=15.6U +PD=17.4U .ENDS core__cell2 *** TOP LEVEL CELL: core_cell2_sim{lay} xcore_...@5 Out b GND in+ in- VDD core__cell2 * Spice Code nodes in cell cell 'core_cell2_sim{lay}' .include C:\Electric\C5_models.txt VDD VDD 0 DC 3 Vgnd GND 0 DC 0 vb b 0 DC 1.33 Vin+ in+ 0 DC 0 SINE 1.5 100m 1k Vin- in- 0 DC 0 SINE 1.5 -100m 1k .tran 0 2m 0 .1u .END This is what I have. Thank You Regards Weiyi On Mar 10, 1:22 am, war_of_justice <[email protected]> wrote: > Hi all > > I have tried to implement a layout model consisting of several p and n > mos. My layout is able to simulate out some result and reading. > However, when I compared the result of the layout with the schematic > form, the result varies slightly. When I tried to write the spi file, > the notepad willl show the ttransistors parameter, for some of the > transistors, there is a +PD= some value inside each line and it is red > in colour. May I know whether the red +PD indicate an error and how > can I go about correcting the error? Currently, I am using the model > of C5_models for the transistors. > > Thank You > > Regards > Weiyi -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
