Hi, To check the well connections go into File -> Preferences -> Tools -> Well Check and select the appropriate parameters.
I am unsure why the Spice generated netlist doesn't show that top device's body connected to the output, maybe Jan or a developer can comment. In your schematic you have two NMOS devices, one with a body connection shown and tied to the device's source, and one with the body connection not shown indicating the body is tied to ground. This design must be fabricating in a process that uses a p-well since in an n-well process the substrate is used for the body of all NMOS devices and is grounded (so you can't lay the NMOS device out in its own well). Good luck, Jake. On Fri, Mar 12, 2010 at 8:35 AM, Sudipta Sarkar <[email protected] > wrote: > Hi, > > I am attaching the .jelib file. > Regards, > Sudipta > > Sudipta Sarkar > Contact No: +91-9482088380 > M.E. Microelectronic Systems > Indian Institute of Science (IISc) > Bangalore 560012 > > > On Fri, Mar 12, 2010 at 8:40 PM, <[email protected]> wrote: > >> Are you connecting the body in the layout to the proper node? There are >> 4 connections on the layout device as well. >> >> >> >> Jan >> >> >> >> *From:* [email protected] [mailto: >> [email protected]] *On Behalf Of *Sudipta Sarkar >> *Sent:* Thursday, March 11, 2010 6:55 PM >> *To:* [email protected] >> *Subject:* Re: Electric VLSI design system doubt >> >> >> >> Thanks, >> >> 1. Now I am using 4 port transistors in the schematic...So when I try to >> write the spice deck from schematic, it is correctly connecting the body to >> its source. However if I try to write the spice deck from the layout, the >> body is being connected to ground for NMOS and Vdd for PMOS, even if I do >> the connections otherwise. >> >> 2. I think that in NCC the well connections are not checked, is that >> true.? >> >> 3. Should I attach my library file? >> >> Regards, >> Sudipta >> >> Sudipta Sarkar >> Contact No: +91-9482088380 >> M.E. Microelectronic Systems >> Indian Institute of Science (IISc) >> Bangalore 560012 >> >> On Thu, Mar 11, 2010 at 7:45 PM, <[email protected]> wrote: >> >> 1. I will presume that you are doing this because your design requires >> that it be in its own well. Then you are subject to the design rules >> for well dimensions. >> >> 2. You must make sure in your schematic view that you use a 4 port >> device not a 3 port device. Then you can connect the body to the >> source. >> >> 3. See answer to #2. When you select the transistors from the list >> you'll notice a small triangle in the selection box. Click, I hate this >> as a verb, on the triangle and you'll get more options. >> >> >> Jan >> >> -----Original Message----- >> From: [email protected] >> >> [mailto:[email protected]] On Behalf Of sudipta >> Sent: Wednesday, March 10, 2010 9:41 PM >> To: Electric VLSI Editor >> >> Subject: Electric VLSI design system doubt >> >> >> >> Hi All, >> >> I want to connect the body of one PMOS transistor in my design, to its >> source. The problems >> I am facing with this are the following, >> >> 1.I use the mocmos technology. It places a large well around each >> transistor....consequently >> as the wells of other pmos transistors and this particular transistor >> has to be isolated,it takes up >> a large area. Is there any way to reduce this area requirement? For >> example, can the default >> well area around each transistor be reduced. >> >> 2. Even if connect the body of a pmos to its source, while writing the >> spice deck, it connects the body to >> power. >> >> 3. In my schematic view I get option to use 4 port nmos transistor, >> but no similar option exists >> for pmos transistor. Consequently there is an ncc error between the >> layout and schematic. >> >> >> Thanks, >> Sudipta >> >> -- >> You received this message because you are subscribed to the Google >> Groups "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]<electricvlsi%[email protected]> >> . >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]<electricvlsi%[email protected]> >> . >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. >> >> >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]<electricvlsi%[email protected]> >> . >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]<electricvlsi%[email protected]> >> . >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. >> > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > -- http://CMOSedu.com/jbaker/jbaker.htm -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
