As Jake mentioned, there is no difference between the source and drain when
you lay out the circuit other than what is attached to the well.  Are you
assigning the names to the pins so that they match what you want on the fets
that are mirrored?

It may be that the fet you are using as a starting point has these named and
when you mirror them they are backwards.    If you want the source and drain
named correctly I would say create one that has them prenamed and the spice
model attached and then when you rotate/mirror them make sure that the S/D
is in the correct position.

If it helps add the arrows to the device you create to keep track of what is
what.  Then you can quickly create a schematic of your circuit.  I found
this to be useful as I am used to seeing the arrows on discrete components.
It took a while to realize that in Electric there is no difference and to
not need the arrows or source/drain labels.

Ed

-----Original Message-----
From: [email protected] [mailto:[email protected]]
On Behalf Of Augusto
Sent: Wednesday, March 24, 2010 5:26 PM
To: Electric VLSI Editor
Subject: Re: Problem with drain/source position

Hi Jake,
i'm doing a differential pair ( with w=300), so i'm using a parallel
configuration to emulate a transistor with that width and the cross-
over tecnhique. I need that all of the transistor might be in parallel
(same drain node and same source node). The problem is that i'm laying
out a polarization circuit too, so i spend a lot of time changing the
positions manually!

Regards.

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