On Apr 17, 12:26 am, Mark jones <mark.jones...@gmail.com> wrote: > Hi all, > > I wanted to simulate my transistor level schematic. But I cant do with > the conventional voltage sources (pulse, pwl). > > is there any other way I can simulate my schematic. I was thinking of > writing testbench in verilog. > > how can i do this with electric. Please help me > > thanks
if your schematic contains only pmos/nmos transistors, you can generate the verilog netlist and write a testbench. however, you will only be doing switch-level simulation in verilog only (i.e., 1/0). other devices won't work. it is strange that you can't use spice for simulation. it provides many different types of voltage/current sources - which should work in the majority of cases... provide a better description of your problem. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to electricv...@googlegroups.com. To unsubscribe from this group, send email to electricvlsi+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
