Hi, Even for Nwell processes (ie processes that do not have Pwells), MOSIS recommends the use of Pwell layer in layout where-ever the layout designer wants P-substrate to be present. Although this is ignored by MOSIS during mask creation but still it helps in preventing some common layout errors and might also be useful for Design Rule Checks for some processes.
Rajat On Sun, Aug 8, 2010 at 5:07 PM, MMGhauri <[email protected]> wrote: > Why are there both n and p well in the Electric VLSI program when > using the mocmos (maybe for others too)? Isn't only a single well > needed? e.g. for a p-substrate process, we don't need a p-well for an > nmos. Why do we have to draw it(the n-well is compulsory for the > pmos!)? > > Regards > MMGhauri > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
