I was talking about the second scenario, unfortunately. I suppose the best I can do with Electric is draw it in that program to make sure my circuit works, then copy the design into Xilinx ISE so I know that it's Xilinx's fault if it doesn't work, and not my design.
Are all the vendor programs really equally bad? Is there any one of them that is even remotely reliable? I considered switching to Altera, but I would have to buy a new board for it, and I don't want to make that investment unless I can be sure it will work better. On Nov 17, 12:53 pm, John Porche <[email protected]> wrote: > This is a big question - but basically you _can_. > What you are talking about is fpga (or cpld) prototyping of ASIC > designs - I think. > > Not withstanding device capacity - most digital designs can be > implemented in programmable logic as well as on an ASIC. > Some design flows encourage prototyping the ASIC design in > programmable logic first, then moving to the ASIC when > performance/production/cost dictates. > > But I suspect what you are really asking is: > Can Electric be used as an FPGA CAD environment. > simple answer: no > To make the files needed for CPLD's and FPGA's you need a synthesis tool. > This tool can take structural and/or behavioral HDL (verilog and VHDL > for instance), and translate the code into the required configuration > files of the programmamble logic. > > this is no small task. and not something electric can do. > > Logic minimization, tech mapping, place and route, must be figured out > by the synthesis tool - not to mention timing and other constraints. > > Synopsys makes an FPGA synthesis tool, as well as just about all the > programmable logic chip vendors (theirs are usually free for students > - non-comercial). > > The vendor-supplied tools tend to be crap, however. > > While I WISH someone would start an open-source synthesis tool that > could do programmable logic, ASIC std cell, and maybe even regular > circuits, I haven't heard of one started yet. > > If you want the nitty gritty: you could download from xilinx all of > the data sheets , and use the MVSIS tool from UCBerkely to map HDL-> > FPGA, but I suspect it is much easier to just use the vendor supplied > crappy/buggy tools. > > cheers > john > > > > On Wed, Nov 17, 2010 at 10:02 AM, John <[email protected]> wrote: > > Thanks for your help! > > > A few questions: > > > I have a Coolrunner II CPLD board, are you saying that there is some > > way I can translate a circuit built in Electric into a Coolrunner > > 2 .jed file? The coolrunner II board is quite old, so that might have > > been one of the types they released the details on. > > > Or, are you saying I should make the circuit in electric, and somehow > > translate it to something Xilinx can understand, and have it make > > the .jed file? > > > You might have answered it already, I'm having trouble following you. > > I don't know much about how this device works, I just started in > > digital logic. > > > -- > > You received this message because you are subscribed to the Google Groups > > "Electric VLSI Editor" group. > > To post to this group, send email to [email protected]. > > To unsubscribe from this group, send email to > > [email protected]. > > For more options, visit this group > > athttp://groups.google.com/group/electricvlsi?hl=en. > > -- > --------------- > John Porche -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
