So I am trying to find in[1:32][A][new] in the layout. When I search for in[*][A][new], "nothing found is returned". It must be simple, for some reason I can't figure out where I am doing wrong!.
-nav On Mon, Dec 6, 2010 at 1:45 PM, Steven Rubin <[email protected]> wrote: > The "Edit / Text / Find Text" command searches the current cell for given > text. It can replace, do wild-card searches, and more. > -Steve > > At 01:37 PM 12/6/2010, you wrote: >> >> Thanks Steven, I tried the first workaround, seems to be working. Also >> is there a way to do wildcard (*) search or, search and replace in >> electric? >> >> Thanks again! >> >> -nav >> >> On Dec 6, 12:51 pm, Steven Rubin <[email protected]> wrote: >> > At 12:30 PM 12/6/2010, you wrote: >> > >> > >> > >> > >> > >> > >Hi All, >> > >> > >I have a schematic that includes bus exports. I would like to extract >> > >the verilog code and run verilog simulations. I noticed that when I >> > >extract the verilog code from Tools --> Simulations(Verilog) -> Write >> > >Verilog Deck, the bus index format is not preserved. For example: >> > >> > >the schematic has an export in[1:32][A][new,old], when electric writes >> > >the verilog deck, the ports are now type reg but 1-bit like >> > >in_1_A_new, in_1_A_old, etc. >> > >> > >I am wondering if there is a way that I can make the verilog code to >> > >say reg [1:32] in_A_new, in_A_old etc. And I tried checking the >> > >verilog preferences for "preserve verilog formatting" and >> > >"parameterize verilog module names", its still the same. I appreciate >> > >any help or suggestions. Thanks >> > >> > I believe that the problem is that Verilog does not allow >> > multidimensional arrays. Therefore, it is not possible to preserve >> > signals that have names like in[1:32][A][new,old]. >> > >> > However, there *is* a workaround, because the Verilog netlister will >> > convert the early parts of a multidimensional array and leave the >> > last part intact (if it is numeric). Therefore, if you had a bus >> > that had the name >> > in[A][new,old][1:32] >> > (note that the numeric part is the LAST index) then the Verilog >> > netlister would convert this to: >> > in_A__new_[1:32] >> > or something similar. >> > >> > Another thing that you can do to make this work is to "alias" the bus >> > to one that is simpler. >> > For example, create two connected bus segments and name one of them >> > in[1:32][A][new] >> > and the other: >> > inAnew[1:32] >> > Now these two busses are both 32-wide and are effectively aliased >> > because they are on the same network. >> > Now Verilog is happy to use the bus "inAnew[1:32]" because it is not >> > multidimensional. >> > >> > -Steven Rubin >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]. >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]. > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
