I have a project that asked to build a SR-Latch i did it using nor gates but when i simulate the shematic it looks diffirent that the one from the layout .why ?
if u want i can sendu the file to check it .. because as far as i know everything is correct in my lyout ! -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to electricvlsi@googlegroups.com. To unsubscribe from this group, send email to electricvlsi+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
