I made a layout of a simple transconductor(OTA) in Electric. After simulating the netlist from layout I observed that no parasitic capacitances were extracted(I checked the settings in Preferences- >Tools->Parasitic). What to do? Also after simulating the netlist obtained I got a totally different AC response for the OTA(normally its a low-pass-single pole system.) In many places the drain and source were interchanged as desired(what is the technique for getting desired drain/source?). Also after editing the netlist to get same drain source combinations still the response was way different than desired. Will the nmos/pmos locations matter (like placing an nmos above or below a pmos) in the final netlist and the response??
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