Hi I am design a general propose adc in electric from J. Baker's book. I have made the schematic and everything its ok.
After that i went to tools -> Silicon Compiler -> Convert current cell to layout. The electric returns me a hole list of layout designs with and2, nand ....gates. One of them called rdff seems to be the hole schematic structure. I will like to ask if rdff layout its the totally conversion layout generated from schematic cell. Thanks to all Chris -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
