Ok, I got the idea of appended file. It is similar to adding spice code on the schematic or layout window. I don't know about what 'level' corresponds to, but according to ELECTRIC manual( Help> User's Manual), section 9-4-3, it is not used anymore. "
- *Spice engine* Can be Spice 2, Spice 3, HSpice, PSpice, Spice Opus, Gnucap, or SmartSpice. - *Spice level* Can be 1, 2, or 3 (not used anymore). " http://cmosedu.com/cmos1/ltspice/ltspice_electric.htm , may be relevant to you. Good Luck ! On Mon, Jun 10, 2013 at 1:32 PM, Usama Awais <[email protected]>wrote: > Thanks a lot Ayatullah, the user_append file is the one which is needed to > provide a stimulus to the extracted circuit spice deck from Electric...I > have attached the snapshot. what is meant by spice level..(there are three > levels when you scroll down), certainly it is not the device level which > has reached to a large number. > > > On Saturday, June 8, 2013 9:28:43 AM UTC+5, Usama Awais wrote: >> >> Hi everyone, >> >> I was using Electric with LT SPICE for designing a flash ADC and had a >> few queries. These issues have been disturbing me for quite a while! and >> hindering my work. >> >> Does changing the process alter device parameters as in the models being >> used or is the process and device model file completely independent of each >> other? >> >> Does Changing the technology scale/process alter W/L ratios etc? >> >> Lastly I would like to mention that I have 4 files, 180nm_bulk.mod.pm, >> 90nm**_bulk.mod.pm <http://90nm_bulk.mod.pm/> (arizona state predictive >> technology model), scmos25.mod and user_append.spi. I know the >> user_append.spi is used and needed to give the circuit a stimulus. I even >> know that 180nm and 90nm files are separate pm (parameter files). I cannot >> figure out what scmos25.mod is since its contents vary slightly from the >> 90nm and 180nm file. While generating a SPICE deck we give 2 files >> scmos25.mod as the header card and user_append.spi as the footer card in >> Electric VLSI Design system preferences. What I dont get is the >> difference between scmos25 and either of the 180nm and 90nm files. How do >> we define what model is being followed in LTSPICE while generating a SPICE >> deck from Electric VLSI tool. Does setting the technology scale >> predefines it (on the other hand my technology scale in electric is >> 125nm). >> >> This whole bunch of stuff is all mixed up and confused. I am also >> attaching these files for reference.I would be happy for clarification. >> >> Regards >> Usama Awais >> > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/groups/opt_out. > > > -- Best Regards, *MOHAMMAD A MAKTOOMI,* *PhD candidate, ECE* *IIIT-D, **INDIA.* *www.maktoomi.blogspot.com http://iiitdelectronics.blogspot.in/ * *Contact- **+91-* 97 18 140152 "If you want the love of people, stop running after it. The more you chase it, the more it escapes you. Love doesn't come from the people, it comes from Allah". -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
