Hello Everyone: I don't know if you have faced the same problem: when writing the Spice deck on Electric VLSI for simulation on LTSpice IV, I noted that the extracted drain and source areas (AD, AS), as well as drain and source perimeters (PD, PS) do not match with the real values for these dimensions.
Is there any way to fix this problem? Regards, Estevao -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
