<https://lh3.googleusercontent.com/-XR8d1uUb3QU/WkUp_UQTiPI/AAAAAAAAAJo/a_q1dCUiQ-8bM6VL4FnEU6LhVE7u58ddQCLcBGAs/s1600/Asic%2Bproject.JPG> Hi,
i am trying to implement a task that follows Synthesis --> Floorplanning --> placement --> Routing i am exploring many options i need urgent guide how to load verilog file and synthesize it will higher abstraction level of verilog file code work for it? or we have to provide a verilog code working at gate level ? how to synthesize it? and go to floorplan stage. i am getting a lot of errors while loading a verilog file. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
