Thank you Gavin for the reply. I already found the example you suggest but I couldn't work it out because I'm trying to do the place and rout starting from schematics. Right now I managed to get the auto-route working, but I still need to manually place the cells I'm going to you in the layout. Shouldn't this be automated?
On Wednesday, February 7, 2018 at 2:24:13 PM UTC+1, Gavin wrote: > > No, the Electric manual is the most complete reference that I know of > for that. > > For the "Old Way", there is an example "Electric VLSI Silicon Compiler > Verilog.pdf" that you should be able to find in the Google Groups > "Electric VLSI Editor" archive at: > > https://groups.google.com/forum/?hl=en#!forum/electricvlsi > > Look for a post with the subject "Re: Physical Design from Verilog File > to synthesis - floorplanning - placement" on 12/30/2017. > > On 2/7/2018 4:08 AM, Andrea Bettati wrote: > > Hi to you all, > > I'm doing a small project for my Digital Design course. The goal is to > > build different adders circuits and compare their performance. > > I built my cell library and now I need a fast and reliable workflow to > > perform the place and route. > > I read the manual but I got stuck in both using the "Old Way" and the > > "New Way". > > Is there a more complete reference? > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
