I guess that the recognition of resistive layers is not needed for
modelling parasitic capacitance of resistor to ground. We can just set
value for per square parasitic capacitance for resistor as whole.
As long as we set resistor parameters as W/L we can do it without
significant changes of the code.

Still I'd like to play with it later because I can use other PEX extractor
tools (QFLOW oar Calibre) on my GDS.



On Fri, Jun 18, 2021 at 9:30 AM <electricvlsi@googlegroups.com> wrote:

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> Alexandre Rusev <cyberf...@gmail.com>: Jun 17 11:25AM +0300
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> >They certainly don't recognize resistive poly layers.
> Okay, I'll think on approach to add this feature. I need to
> understand algos of resistor parasitic capacitance
> extractions, used by other tools...
> Is the technology->factors->Minimum Resistane the value presumed to be used
> for
> splitting resistors into "lumped resistor elements" before inserting
> parasitic capacitors to ground?
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