Hello everyone, I have three questions and would appreciate any help with them:
1. Is it possible to set Electric to not put the library name together with the cell name in a subcircuit? I only find this discussion: https://groups.google.com/g/electricvlsi/c/q6skY672BSs/m/6AJI3L_y0h8J , where is stated that this would be the standard of Electric. No mention if it's possible to control it. I couldn't find any preferences directly related to it. Am I missing something? 2. Is there any way of making Electric aware of the current densities in the contacts, vias and tracks? Like the DRC, but related to this issue? Any ideas to make it available? 3. Does anyone here know the C5N, TSMC 180nm or IBM 130nm (all former MOSIS) permitted current densities? I've been looking but still didn't find it through the internet. I found something about 0,5 mA/um for metal tracks (only) as a tip, nothing from process info. Found numbers for other processes (non MOSIS) but not for those. Thank you in advance. Best regards, -- Patrick Mendes dos Santos, Professor, M.Sc. Departamento de Engenharia Elétrica / Electrical Engineering Department Federal Center of Technological Education of Minas Gerais (CEFET-MG). Campus II, Av. Amazonas, 7675, Nova Gameleira. CEP: 30510-000. Belo Horizonte, Minas Gerais. Brazil. Phone: +55 31 3319 6834. e-mail: patrickce...@gmail.com Website: http://www.eng-eletrica.bh.cefetmg.br/ <http://www.engenhariaeletrica.cefetmg.br> -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to electricvlsi+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/CACog4cFOKSsFeEp0sGLZxOCbvJf3UPYmuReviDvBtnQJMxiunA%40mail.gmail.com.
