Hello all ! See subj ;)
Our team doesn't have a lot of practice in ASIC design. (Not only because latest political events, but also because the same trend was observed before in our location) My effort of setting up Electric tool for our particular PDK is breaking about inability of our team to make exaustive testing of setup vs. other analog layout tools we use and calibre setups. (The problem makes even worse with archaity of available 180nm PDK, and the fact that we lost our active ASIC design projects) If any team, using Electric for regular tapeout their ASIC projects having issues with the tool itself I can try to help Steven to solve their particular issues in SW. Yet I need access to real problematic examples (and to real tech-desc files for Electric). If our community can help me with it, I'll be able to contribute to SW ool development more efficiently. If NDA-s and so on need to be signed - I am ready for that. So I offer to help me to be more involved... Best wishes, Alex PS: Looking forward for feedback from interested ASIC development teams -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to electricvlsi+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/CACoSTqLuS%2BC5deN5U34O_0AgfTPefQjfzi0YppB2JSqv1AwvMA%40mail.gmail.com.