> On Oct 31, 2017, at 5:32 PM, Kaushal Modi <kaushal.m...@gmail.com> wrote:
>
> On Tue, Oct 31, 2017, 7:14 PM David Rogoff <da...@therogoffs.com
> <mailto:da...@therogoffs.com>> wrote:
> Hi.
>
> Hello.
>
> I’m trying to clean it up by using orgmode macros. However, it seems like
> these are not replaced when inside code blocks.
>
> Do you have a minimal example of what you'd like to "macrofy" in the verilog
> code blocks?
Pretty simple text substitution. Something like this:
#+MACRO: SEC_HDR1 // ---------------------------
#+MACRO: SEC_HDR2 //
#+MACRO: SEC_TITLE This section declares local types and constants
* File 1
** Section 1: {{{SEC_TITLE}}}
#+BEGIN_SRC verilog
{{{SEC_HDR1}}}
{{{SEC_HDR2}}} {{{SEC_TITLE}}}
parameter A = 1;
#+END_SRC
So SEC_TITLE expands in the headline and also as a comment in the tangled
verilog code.
It would be really great to be able to embed newlines in the macro to it could
be one line / macro in the src block.
>
> Probably the solution is to use noweb references with arguments? See the Org
> manual.
Thanks - I’ll have to look into noweb. I’m not familiar with it.
David
