Alexey Starikovskiy pravi: > Slavko Kocjancic пишет: > >> Alexey Starikovskiy pravi: >> >> >>> As a matter of fact, I already see a big stopper in your board usefulness. >>> You put optical isolation between logic and parallel port, I see 2 >>> drawbacks of it: >>> 1. parallel ports are quite weak these days (3.3v/~5mA), so driving LED >>> from it directly is not bullet proof. >>> >>> >>> >> All EPP ports are 5V tolerant and I didn't see the EPP port diferrent as >> open colector with pullups. LED are arranged to be driven low with >> external 5V supply. And optocoupler is happy with anithing from 5mA up >> to 20mA. So I see no problem. >> >> > Parallel port can take 5v as input, it can't output 5v, only 3.3v. And > it's ability to > supply current is near 5mA, so your design is at the edge. > I'm talking that I need to sink at least 5mA. The problem with 5mA @ 3.3V are in board when LPT port need to source that curent. I'm done that so many times and never has problem. ...and work mostly on laptops.
>>> 2. on both sides you have logic levels _always_. >>> >>> >>> > There is little sence to put isolation _here_. > Here is only to have cheaper board! (much les optocouplers nedded) >>> 3. machine equipment on the other side of your logic has very different >>> set of voltages, >>> 12, 24 volts are common, and sometimes you could find 48, your board >>> does not allow to >>> connect this equipment without yet another layer of optical isolation. >>> >>> >>> >> I'm setup machines without problems on that. The board need 12V >> unregulated for relays only If you have no relay then anithing betwen 8V >> to 30V is good. >> >> > I'm talking about inputs, are they capable of accepting 24v? > No they don't. But on near all hobby machines here are just some endswitches and similar things. So why bother with 24V? >>> 4. now you have common ground between all your logic and all 48 inputs >>> and outputs >>> (and your schematics can be stretched to 160)... I doubt that you could >>> keep such ground >>> clear of the machine noise. >>> >>> >>> >> The bad design has big ground loop noise. If somewhere is that problem >> then just put normal optocoupler just here. >> >> > you get 160 signals returning to the same ground, I call it bad design > by definition... > And yes, your optocouplers are needed here, not between parallel port > and the logic. > the board is made for 24 signals. >>> In general, your design seem to be very close to UBOB board here: >>> http://www.candcnc.com/UBOB.htm >>> >>> >>> >> Seems similar. But my board rely on EPP interface to not stall computer. >> One cycle LPT port take near 1uS! And I need only 1 per byte. UBOB needs >> at least 3. And price is way overpriced. All thing for my plate is >> under 25Eur. (with homemade pcb) >> >> >>> The problem with the above seems to be it's price, for about same money >>> its possible to >>> get much more capable board from MESA -- 7i43. >>> >>> >>> >> Yes MESA is good ... .. but without isolation at all! >> >> > So put your isolation after the MESA, properly done it will have much > more value, > than your current board. Only it's size makes it prohibitive. > >> Any time I have problem with ground loop problem the relation PC <--> >> Machine is the worst one. >> >> Anyway I don't want to argue is it good or is it bad. Just want simple >> solution for simple benchtop machine. >> >> > I thought you were thinking of the board, which might be useful to someone > beside you and your simple benchtop machine. > Regards, > Alex. > > Just that... As I surf the web to find some usable I found nothing. So I decide to make one and to publish all documentation and instruction how to build it. For that reason there is no CPLD/FPGA/CPU.. as all need some kond of programming. And I write here just to get some help how to make driver for that board. As protocol is simple then more board can be made with same software. (and to have optoisolation in different place too)... Slavko. ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
