On 11/11/2012 1:38 PM, Michael Haberler wrote:
> Am 11.11.2012 um 18:43 schrieb Kent A. Reed:
> <...>
>> Curiously, I get better jitter results on the quadcore if I run both
>> latency-test threads on cpu 0, e.g., a core that is exposed to the Linux
>> scheduler, than on isolated cpus 2 and 3. On the other hand,
>> latency-test running entirely on cpu 0 is somewhat more sensitive to me
>> starting other processes, like glxgears, but the effect seems to be
>> restricted to a few microseconds accumulated the first time I start up
>> glxgears (maybe due to fetching glxgears from the disk?---I should try
>> again with a solid-state disk).
>
> these results puzzles me as well.

> one thing I cant make sense of yet is:
>
> isolcpus=1 on an atom
>
> bind base-thread in latency-test to cpu1 (the isolated one) and servo-thread 
> to cpu0 (where linux runs too) and I get consistently lower latencies on 
> servo-thread than on fast-thread
>
> making sense? none I can see..

I could explain both your observation and mine if I could come up with a 
mechanism that causes the jitter to be higher on a lightly loaded cpu 
than on a heavily loaded one. In both our situations, cpu0 is running 
other processes besides our RT threads.

In the early days of EMC2, "the cache" was proposed as the problem with 
a lightly loaded cpu, where "other processes had enough time to replace 
the RT code in cache between invocations of the thread." Improved 
real-time performance with cpu hogs running was  taken as proof of the 
conjecture. It made sense to me at the time.

I don't know what to make of this conjecture in the case of isolated 
cpus. I thought if they were isolated from the Linux scheduler, then no 
processes would be loaded to them unless we loaded them explicitly. Is 
there something going on in Xenomai that could be causing this? (Note 
that I haven't tried this with the RT-PREEMPT alternative). Could it be 
that my naive picture of the multicore chip architecture in which each 
core has its own cache is wrong and the cores share common cache so that 
activity on one core could cause another's idle process to be flushed? 
(Note to self: go find out!)

Regards,
Kent


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