On 12/3/2012 6:44 AM, Charles Steinkuehler wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 12/2/2012 10:22 PM, Michael Haberler wrote: >> I have several starting points and 'just' need to determine which >> one works well. 'Just' should be read as 'a kernel build for such >> platforms should be started before you go to sleep, and check in >> the morning'. > Note that you can easily cross-compile kernels...building Linux > natively on these ARM boards is painful, and on many systems capable > of running Linux it's just plain impossible (at least without massive > upgrades to available memory/disk). > > I haven't experimented with cross-compiling LinuxCNC. That's more > mountain than I want to climb right now. :) > > <snip> > >> As for the Raspberry: that has very limited potential - the >> platform is about half as fast as the Beaglebone, has fairly >> minimal GPIO, and it is wed to the Broadcom chipset, which I would >> rate as a company which still doesnt get it. A mean voice said >> about the chipset used on the Pi 'half of it isnt documented, and >> the other half doesnt work'. Thats not entirely true but there is >> something to that comment. > Even worse, the Pi isn't an ARM chip with a bunch of stuff attached, > it's a black-box video decoder/GPU that happens to have an ARM as a > co-processor. The GPU is in total control of the system (including > booting from flash), everything about the GPU is undocumented, and the > GPU can eat up as much bus/memory/system as it wants, holding off even > a real-time Linux kernel for unknowable amounts of time. > > I agree with you that Broadcom doesn't get it, and TI does. > > - -- > Charles Steinkuehler
Some thoughts... http://www.ti.com/lit/ug/spruh73g/spruh73g.pdf documents the processor used on the BeagleBone. After looking at it (over FOUR THOUSAND PAGES), I've concluded that TI really does get it. In vast detail. 1 -- The chip has a built in three port gigabit ethernet switch. And supports ethernet timing synchronization. (Some sort of real time ethernet.) 2 -- It has three enhanced quadrature decoders. The decoders can timestamp transitions so as to support speed estimation at low speeds. 3 -- It has three (I think) fancy PWM generators. 4 -- There are multiple DMA channels, modes, etc. I'm sure they can be used with the ethernet interfaces, but only guess that they can be used with most other peripherals. I haven't gotten to the section on PRUs yet, but from what Michael has posted, it seems that they can toggle bits way faster than needed for steppers. If I were building a product that was LinuxCNC like (or that integrated with it, or used parts of it, or ...) I would strongly consider this processor. I have a feeling that much of the stuff done in FPGAs by Jon and Peter are already built in. I'd probably look at how I might tie multiple devices together using the fancy ethernet so as to support additional axes. ============ It's not at all clear to me how we get there from here. My guess is that if we want to use the PRUs, we will need to develop some sort of hardware driver abstraction layer to achieve portability. (That's if we don't want to have two independent sets of drivers.) Does someone have a pointer to a decent document with an overview on the TI chip? I'd actually like a few different ones. A 40 page overview followed by a 400 page detailed document would be great. The 4000 page document could then be used as a reference to get the details of relevant registers as they are needed. Regards, Ken ------------------------------------------------------------------------------ Keep yourself connected to Go Parallel: BUILD Helping you discover the best ways to construct your parallel projects. http://goparallel.sourceforge.net _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
