On Sat, 4 Oct 2014, Chris Morley wrote:

> Date: Sat, 4 Oct 2014 18:23:41 +0000
> From: Chris Morley <chrisinnana...@hotmail.com>
> Reply-To: EMC developers <emc-developers@lists.sourceforge.net>
> To: EMC DEV <emc-developers@lists.sourceforge.net>
> Subject: Re: [Emc-developers] Pncconf in master
> 
>
>
> Thanks Peter it really helps.
> A few questions:
>
>>
>>
>> A couple things:
>>
>> loadrt probe_parport
>>
>> should probably only be inserted for RTAI (and maybe only on EPP configs)
>> It fails on uspace
>>
>
> I wonder if this would be considered a bug?
> IIRC our docs say using probe_parport when not required is benign.
> I guess if we can, we need to fix this with uspace or change our docs.
>
>
>> PID stepgen works (tried on 7I76E, made a 5i25/7i76 config and replaced 5i25
>> with 7I76E and changed driver line)
>>
>
> Does the 7i76E, in general come with the same firmware as the 7i76?

The 7I76E is basically a 7I76 grafted onto a FPGA card (with 3X 17 I/O ports) 
one of which (IO 0..16) is dedicated to the attached 7I76

> Is there also a 7i77E?

Not yet but working on it

> If so I will add that to pncconf's internal firmware.
> I'm sure I can find a sample config to follow the driver line
> or check the man page.

loadrt hm2_eth board_ip="10.10.10.10" config=" num_encoders=1 num_pwmgens=0 
num_stepgens=5"

for example (IP address may change of course)
>
>> if the DPLL module is present, the following lines can be added to reduce
>> stepgen jitter:
>>
>> #add these lines if you have a DPLL module
>> # set timer 1 to 50 usec before servo thread
>> setp hm2_CARD.0.dpll.01.timer-us -50
>> # enable DPLL timed latching of stepgen position
>> setp hm2_CARD.0.stepgen.timer-number 1
>>
>> with the DPLL module you can have a much higher PID P term (since the 
>> sampling
>> jitter is reduced by a factor of ~10 to 20 times)
>>
>> P = servo thread rate works well for me with DPLL (so 1000 for 1 KHz, 2000 
>> for
>> 2 KHz etc)
>>
>
> How would one test for the DPLL module being present?
> Is it depended on just using master or are there firmware updates to hardware
> needed?


Its only in some firmware (currently all firmware with DPLL has a D in the 
file name like 5i25_7i76x2D.bit)

Its mainly needed for Ethernet/Preemt-RT to be able to run high speed (1200 
IPM or faster), high accell stepgens while tolerating significant jitter (say 
100 usec or more) and still allow small ferror limits

you can test live for any of its pins being present:

hm2_CARD.0.dpll.01.timer-us
hm2_CARD.0.dpll.02.timer-us
hm2_CARD.0.dpll.03.timer-us
hm2_CARD.0.dpll.04.timer-us
hm2_CARD.0.dpll.base-freq-khz
hm2_CARD.0.dpll.ddsize
hm2_CARD.0.dpll.phase-error-us
hm2_CARD.0.dpll.plimit
hm2_CARD.0.dpll.prescale
hm2_CARD.0.dpll.time-const


>
> If DPLL is available is there any reason to NOT use it?

Its almost always a good thing especially with jitter noise that has limited 
energy (most RT jitter is like this), I will add Encoder latching next

>
>>>
>>> Feel free to PM me on bug reports or suggestions.
>>> Thanks.
>>>
>>> Chris M
>>>
>>
>
>
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Peter Wallace
Mesa Electronics

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