On 6/20/20 7:26 AM, andy pugh wrote:
I have been wondering this for ages, why is one of the Limit3 tests called "sunny-day"?
That's a term from a day job I had years ago - a "sunny-day" test exposes the component-under-test to normal, expected conditions, ie it verifies that it does the right thing when everything else in the world is going well.
This is in contrast to the more common test where the component is exposed to stimulus at the edge of its envelope, or outside its envelope, and the test verifies that it degrades or fails gracefully.
-- Sebastian Kuzminsky _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
