Walter Based on my understanding of your question and my understanding of the current requirements in 1010, I believe the following is correct.
Clause D does not allow interpolation of clearances in mains circuits, and it states that the creepage must never be less than the clearance (D.2.2). If you look up the clearance I believe it will be 1.5mm (for 300 V) on an uncoated circuit board. If your creepage is not greater than that, then 1.5 is your number. As for the routine dielectric testing, all I can say is I believe that the intent there is to test the spacings, not the component (the varistor in your case). I can't pinpoint where (if anywhere) it is allowed by the standard, but I believe that it would be within its intent to disconnect the varistor for this test. Not that this is convenient for manufacturing, but it is closer to the intent of the standard than reducing the test voltage to what the component can withstand. Richard Payne Tektronix Inc. [email protected]
