Why is it that I frequently get e-mails that have the first letter of
each line missing? Is there anything that can be done about this?
Thanks,
Jim Eichner
Statpower Technologies Corp.
Burnaby, B.C., Canada
jeich...@statpower.com
Any opinions expressed are those of my invisible friend, who really
exists. Honest.
-----Original Message-----
From: sdouglas@anetMHS (DouglasScott){MHS:sdoug...@ecrm.com}
Sent: Thursday, September 25, 1997 8:49 AM
To: dmckean@anetMHS ("Doug McKean"){MHS:dmck...@paragon-networks.com};
JEichner; bceresne
Cc: emc-pstc@anetMHS ("emc-pstc"){MHS:emc-p...@ieee.org}
Subject: RE: EMC Design Question for a Backplane ...
---------------[ Content-type: text/plain; name=Message Body
]--------------
Doug,
I have had the same "discussion" with both the designers and the board
layout
uy. Turns out that our standard proctice is to punch holes for each
connector
in. The holes are usually 0.100" on the surface layer and 0.130" on the
inner
ayers. The result is overlapping holes that end up leaving a large hole
in the
inner layer. The edge of this large hole usually looks serrated due to
the not
completely overlapping holes. Obviously this look will change depending
what p
wers, grounds, signals are connected on any given level.
We have had occaision to go back and modify this approach. This usually
happen
when the designer finds a performance issue during development or when I
have
a compliance problem. In that case we have modified the specific
connector loc
tion, sometimes having to create new pcb layout library components to
make thi
happen. But that is the exception rather than the rule.
We also use other means to address this issue. Any signal to a connector
over
0 MHz usually gets a dedicated connector or a coaxial type. Any signal
from 2
o 10 MHz gets board routing and etch shielding treatments and sometimes
filter
ng. Anything less than 2 MHz gets nothing except as required.
Regards,
Scott Douglas
Principal Compliance Engineer
ECRM Incorporated
Telephone: 1-508-851-0207
Facsimilie: 1-508-851-7016
e-mail: sdoug...@ecrm.com
________________________
__________________________________________________________________________
____
From: Doug McKean on Thu, Sep 25, 1997 12:33 AM
Subject: EMC Design Question for a Backplane ...
To: IEEE Product Safety Technical Committee -
I'm having a lively discussion with one of our
design engineers about backplane PCB design.
Here's the case:
1. Multilayer board, let's say 10 layers,
1 power plane (+5vdc), 3 ground planes,
6 signal planes.
2. Outside world connections to the
backplane with several connectors
across the back of the product.
3. T1/DS1 product.
I want the +5vdc power plane cutaway, actually
well away, from pins of the connectors that do
not use the power plane. I can't draw it very
well with ASCII. But needless to say, if there's
a 6-pin connector with 1 pin using the 5 vdc,
then I want the 5 volt plane cut away from the
other 5 pins with *one* hole.
Instead, what's being suggested is to punch *five*
separate holes through the power plane like a sieve
for each pin not using the 5 volts.
My concern is noise, transients, or ESD coupling
from the outside world lines to the power plane
of the backplane and thus to everything connected
to the backplane.
Am I being too picky here?
What's the standard convention that people
use out there?
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From: dmck...@paragon-networks.com (Doug McKean)
To: "IEEE Product Safety Technical Committee -"
<emc-p...@majordomo.ieee.org>
Subject: EMC Design Question for a Backplane ...
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Date: Wed, 24 Sep 1997 18:16:16 -0400
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