You might want to consider whether the IEC61000-4-4 EFT/B (Electrical Fast Transient/Burst) immunity test needs to be performed on the completed system.
One of the test steps involves injecting 1000V+ transients onto the green wire (protective earth) of the equipment. Connecting your 'ground' (DC circuit common) to chassis provides a convenient path for the transients to wreak havoc on the digital circuitry. Our company makes power supplies, which are too slow to respond to the 5ns risetime/50ns pulsewidth signal. However, the pulses zip through & around our power supply right into our customers' logic. On Fri, 8 Oct 1999 13:50:49 -0400 , "UMBDENSTOCK, DON" <[email protected]>wrote: >Hello Group, > >We are having a debate concerning the best practice for grounding of a >printed circuit board containing digital logic. These boards are >multi-layer with a ground plane and a power plane. > >One school of thought is to tie the ground plane to chassis ground in many >locations, thus reducing the impedance. > >Another school of thought says to control the point(s) that is (are) tied to >ground or risk upsetting of sensitive circuits with an ESD or other immunity >event. The concept is that an ESD event may be decoupled to chassis at the >I/O ground plane with the use of appropriate circuit elements to control >impedances. Now consider the chassis to be steel, and the digital ground >plane to be copper. If the digital ground plane is stitched to chassis in >several locations, it appears that a lower impedance path (copper vs steel) >will encourage the ESD to travel across the ground plane. If the ESD >travels across the digital ground plane, there appears to be a good chance >of upsetting sensitive circuits. So the thought might be to tie only one >point of digital ground to chassis ground, thereby not providing a path for >any immunity event to flow across this ground plane. > >The rest of the above concept is to use moats to segregate key circuits -- >digital, I/O, analog, switch-mode power supplies. Again, some say to keep >the ground plane in tact to provide the lowest impedance reference possible, >so isolation is provided by carving up the power plane. The alternate >approach is to "carve all the way through", i.e., if you have a moat around >a particular circuit, if you are going to isolate, do it for all planes >(stack, do not overlap). This latter approach, however, carves up the >ground plane which would appear to increase the impedance of the overall >ground reference. The argument is that carving up the ground plane is >justified by eliminating the coupling of "dirty ground" to other circuits in >an overlap situation. > >I would like to hear what you do for pcb grounding and why you do it. > >Don Umbdenstock >Sensormatic -- Patrick Lawler [email protected] --------- This message is coming from the emc-pstc discussion list. To cancel your subscription, send mail to [email protected] with the single line: "unsubscribe emc-pstc" (without the quotes). For help, send mail to [email protected], [email protected], [email protected], or [email protected] (the list administrators).
