Here are a set of rules worth recommending:
Engineering design checks:
1 Avoid "spaghetti logic" block diagram. Make certain there's a good flow
of functionality across and around the PCB. This includes using the concept
of transferring INFORMATION not ENERGY (except where one must, like with
clock distribution, but even then, if the clock goes a long way, use a
buffer)
2 ABSOLUTELY check the design for bus "contention". Not the debilitating
kind that stops the functionality, but that pesky little 1 nS of overlap
from sloppy digital design. It's like using two make-before-break switches
for a 3 way light bulb in your home. It will all work, but you will get
some dramatic action at each transition.
PCB Layout:
1 Go on and off the board along one edge as close together as possible.
*IF* a connection must come on or off from some where else make it a high
common mode impedance connection with beads (for dc leads) and common mode
chokes for higher frequency signals. On the PCB reference the trace(s) to
CHASSIS gnd area where the traces have been isolated by going through high
impedances. Bridge between chassis referenced area to PCB gnd referenced
area using the high impedance component.
2 Interleave PWR GND and SIGNAL GND traces at the connectors to lower their
impedances. Particularly high speed lines need their own gnd returns.
3 Use short runs, few "meandering" traces.
4 Bypass caps: use all the same value, the thermal relief pads all the same
dimensions.
5 Have traces maintain good distances between edges and cutouts. [This to
insure a good low impedance ground return path for current.]
6 On particularly "hot" traces include the ground return path and don't
(unless absolutely necessary) "jump" layers. Use 2 traces, if possible and
if you must jump layers (like bus lines) add 2 ground vias around the signal
via.
7 Lower the rise time to minimum speeds with SERIES source terminations.
Use a resistor 22-50 in series plus a bead if you have room. DO NOT EVER
LOWER THE RISE TIME OF A LOW IMPEDANCE SOURCE WITH A CAPACITOR.
8 Keep high speed traces inside the layers, don't route them on the surface,
you'll reduce the radiation by around 14 dB.
9 Stack up the board with traces as close to the GND & VCC planes as
possible (like 4-5 mils even for a 4, or 6 layer board) This will lower the
impedance of the trace *and* reduce crosstalk.
10 Use minimum number of vias to prevent turning the GND & VCC planes into
Swiss cheese. Sometimes blind vias will help.
11 Where the traces for the bus lines turn and jump layers, don't allow
your PCB designer to line up all the vias with the vias so close that they
create a cutout slot! Stagger the vias' positions, or do something, to make
certain there's room for adequate metal between each via.
12 Discourage the use of high speed clocks such as 125MHz, 1.25GHz, etc.
with the argument that using such high speed clocks demonstrates a
designer's weakness because he can't make his design work with slower
clocks. Demand the clock frequency be no higher than 20MHz, because we all
know how to solve those problems. <g>
- Robert -
-----Original Message-----
From: [email protected] <[email protected]>
To: [email protected] <[email protected]>
List-Post: [email protected]
Date: Friday, January 21, 2000 5:39 AM
Subject: EMC Circuit Board Design
>Dear List-Members,
>
>I am requesting information/opinions/etc. on the following:
>
>When circuit boards are designed, what are the common mistakes that the
>circuit board designers make regarding EMC (multi-layer boards in
>particular)?
>
>You can respond to me directly but I would prefer a response to the list as
>I believe that the question is of interest to many on this list-server. In
>either event I will compile the responses and resend the compilation later.
>
>Thanks for your time,
>
>Bob Heller
>3M Company
>
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