Rich,
Multiple zaps and step-stress techniques are ideal for evaluation and
characterization of new circuitry during the engineering phase of
development.
The proof of good engineering design is an ESD test at the system level to
the applicable ESD standard(s). The typical ten zaps may not cover all
logic states, but a sampling plan of several EUT's will increase your
confidence.
IEC/EN61000-4-2 is a 'human body' test and does not advocate multiple
repeated zaps because
1) a human body discharge does not deliver multiple zaps - i.e. multiple
zaps are not a real-world event
2) at air-discharge points where full discharge does not occur multiple
zaps are not practical
3) depending on the circuitry, discharge path heating from multiple zaps
could cause spurious failure modes unlikely to occur in the field
4) for cases where multiple discharge is likely, power-line-crossover tests
are available
As you observed, ESD at the system level is much more stochastic than at
the component level. Alas, the majority of technical publications address
safe-handling techniques and component ESD immunity (my previous ESD
experience was developing protection structures for CMOS and CMOS-SOI
integrated circuits). IEC61000-4-2 and its predecessors are by far the
most realistic system-level tests. Design engineering can simulate ESD
pulses (SPICE or equivalent software) and determine the protection needed.
Prototypes can be tested as you mentioned. The final verification is the
applicable ESD standard.
David Sterner
ADEMCO
Syosset NY
-----Original Message-----
From: [email protected]@PITTWAYNOTES On Behalf Of
[email protected]@PITTWAYNOTES
Sent: Friday, September 28, 2001 8:28 AM
To: [email protected]
Subject: ESD Immunity Testing
Since my last posting on trying to find an ESD expert, I have had to
become
that expert. After reading the ANSI ESD standard and its references, it
is
clear that ESD experts are mostly in agreement on how to correctly
perform
ESD immunity testing. It is also clear test methods in the EN/IEC
specifications do not follow that advice.
ESD testing is a statistical process, so the test methods and the
analysis
of the results must be based upon statistics. There are three basic
causes.
1) The distribution of ESD events in the operating environment has a
non-uniform distribution where the number of expected events per hour is
inversely proportional to approximately the square of the voltage. This
implies in testing that the number of applied zaps in testing and their
levels should also follow this distribution.
2) Digital devices are state machines and some states may be less immune
to
ESD than other states. This implies that each state should be tested.
However, most digital devices have a huge number of states and they
change
very quickly; therefore, the only way to ensure that even most of the
states
have been evaluated is to apply a very large number of zap.
3) There may be a probability distribution for the locations on the
machine
where an ESD discharge is likely to occur. That is, it is not always
equally
likely that a person or an object will come in contact with any given
point
on any given surface.
Statistics can be used to determine the voltage levels that should be
applied and the quantity required at each level in order to provide a
specified confidence level that a machine will have no more than a
specified
number of errors per unit time. However, the number of zaps required is
very
high, usually in the order of one to ten thousand. The drawback, of
course,
it that the testing can be time consuming. However, applying in the
order of
one hundred zaps to a machine according to the EN/IEC specifications
will
provide such a very, very low confidence level that one cannot
reasonably
predict the expected error rate in the field. Worst, the results are not
repeatable since some states may be tested during one test session and
others may be tested during another session. The only predictable case
where
this might not occur would be with a machine with an ESD robustness
level
for all states that are far above the actual test levels.
So here is my question to those of you involved in the EN/IEC standards
-
why have these statistical test processes not been acknowledged in the
standards?
Richard Woods
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This message is from the IEEE EMC Society Product Safety
Technical Committee emc-pstc discussion list.
Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/
To cancel your subscription, send mail to:
[email protected]
with the single line:
unsubscribe emc-pstc
For help, send mail to the list administrators:
Michael Garretson: [email protected]
Dave Heald [email protected]
For policy questions, send mail to:
Richard Nute: [email protected]
Jim Bacher: [email protected]
All emc-pstc postings are archived and searchable on the web at:
No longer online until our new server is brought online and the old
messages are imported into the new server.
