I am hoping someone out there can give me a bit of help. I am currently working on a design for the telecom industry. I need to determine the minimum specifications for setting up my design rules for both internal and external layers and connector selection. According to UL60950 table 2N the minimum clearance that I need to adhere to is .2mm (voltages up to and including 125 V r.m.s or DC). This translates to a .008" clearance. Will this be acceptable?
I also expect that a connector (press-fit) into this board will have to meet or exceed this minimum clearance between any two conductive surfaces or do I need to refer to Table 2K , Pollution degree1 & 2, Voltages under 71VDC 50 Vr.m.s.? Finally almost all specifications are expressed through insulation whether Functional , Basic / Supplementary, or Reinforced. Does this clearance need to grow through air dielectric? Regards, Paul S. Denomme Paul S. Denomme Backplane Design Engineer Viasystems Technologies Inc. Richmond, VA 23235 804-226-5155 ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
