Sir To paraphrase Mr. Mertinooke (previous post in this thread), my testing also goes way beyond requirments of 950 and 1010-based standards, because these standards have not, and cannot keep up with advances in circuit design and materials technology. As very small, hi power-density (e.g., resonate-mode converters) power supplies become more common, as FETs used in the main and PFC converters become more reliable > 70 deg ambient, and as the thermal conductivity of "embedded" materials increases, standards and associated test conditions must change.
I have never seen my employer's designs fail in an unsafe mode in the field; and not necessarily because two or three NCBs/NRTLs/etc said the unit was ok, but because of "internal" safety testing, conducted outside of the scope of any applicable standard, that revealed the actual (potential) safety hazards. Product Safety Test design resulted from system-level simulation and extremes of differential design equations. I did not consider these tests "even more difficult to simulate repeatably". I am concerned that we are wasting our time stressing components that could never fail , other than multiple-fault conditions. I am also concerned that there are products on the market, tested in good faith, that would be unsafe for a more probable SFC, that would not be tested for, in accordance with existing standards. I apreciated you comments, got the grey-matter in motion.. R/S, Brian -----Original Message----- From: Peter L. Tarver [ mailto:peter.tar...@sanmina-sci.com] Sent: Thursday, January 30, 2003 9:13 AM To: emc-p...@majordomo.ieee.org Subject: RE: single fault conditions While s-c and o-c at device terminals do not simulate true fault conditions within components, testing must be practical. If we are to begin considering simulation of true fault conditions within components, there may be no end to the number of tests. Simulation of internal component faults would not only be difficult to establish, but (as Rich Nute alludes) would be even more difficult to simulate repeatably. Then, even if repeatable, how can one be certain that any particular test condition will impose the worst case effects on both the component and the remainder of the interconnected circuitry, leading to multiple simulated faults on a single component. Repeating for each FET, diode, electrolytic capacitor, etc, alternate component vendors, alternate part nos. from the same vendor (even due to obsolescence), the sale of the week that the purchasing agent just made ... would certainly need to be considered. Better to do the oversimplified testing or products would go end-of-life before abnormal condition testing is completed. Regards, Peter L. Tarver, PE
