In a message dated 2/25/2003, Chris Maxwell writes:
What if I were to specify a circuitboard with .006" layer to layer spacing between an SELV layer and a hazardous layer? Obviously, this is less than .016". Furthermore, the drawing would specify to the PCB maker that they must use at least three layers of laminate to make this spacing, for instance, three sheets of .002" fiberglass? Can anybody shoot holes in this design from an EN 61010-1 perspective? BONUS QUESTION: WHAT ABOUT HAZARDOUS/SELV SEPARATION BETWEEN TRACES ON THE SAME, ***INTERNAL*** LAYER? Hi Chris: I work mostly with EN 60950, so I'm not sure how clear EN 61010-1 is on this topic. However, clause 2.10.5.3 in EN 60950 provides a very clear description of what is acceptable for both layer-to-layer and trace-to-trace on the same layer. You might want to read this just to get an idea of what the authors of EN 60950 were thinking. In general, the approach you describe of specifying three layers of .002 inch material would meet the layer-to-layer requirement in EN 60950, but you would always be vulnerable to a screw-up at the board fab house. If your board is a multi-later board, there are a couple other options that help reduce the risk: 1) Put SELV on the top layer and HAZ on the bottom, with no copper on inner layers in that area. This gives you the full board thickness for insulation. 2) If there are several layers in the board, keep one or two layers between the SELV and HAZ void of copper. This provides a simple guarantee that you will always have the desired 2 or 3 layers of thin insulation between SELV and HAZ, regardless of how the board fab house constructs the board. Joe Randolph Telecom Design Consultant Randolph Telecom, Inc. 781-721-2848 [email protected] http://www.randolph-telecom.com
