>From what I can see, UL61010A-1 does not have direct specifications for inner board spacings. Am I missing something - are there guidelines? Section 6.7 basically falls back on surviving the voltage tests..... All the same there has to be some practical guide on how close to allow inner board spacing. I do not worry so much layer to layer but it is the vias that drill down through a ground plane that concern me. That is where the imperfections may show up I figure. If the via circuit is hazardous and requires high pot testing relative to ground plane - how close can the ground plane get to the via? One of my coworkers takes the Basic C&C spacing used for the circuit on the surface of the PCB and divides it in half and uses that value with good results. Thanks Chris Wells
