Chris,
and here is another 10-layer stack-up, if you can give up two of the four fast
signal layers. The improvement here is an extra power plane and the power
planes are close to the top and bottom of the board.
SIG SLOW, GND POUR
GND
PWR
GND
SIG FAST
spaceXXXXXXXXX space
SIG FAST
GND
PWR
GND
SIG SLOW, GND POUR
And another similar stack-up:
SIG SLOW, GND POUR
GND
SIG FAST
GND
PWR
PWR
GND
SIG FAST
GND
SIG SLOW, GND POUR
This stack-up wastes a layer but gets the FAST SIG layers closer to the
top/bottom of the board and gets PWR away from the top/bottom slow signal
traces.
One thing you might find is that the IC's themselves are the big "antennas"
and not the PCB. I am currently investigating this type of thing.
Dave Cuthbert
Micron Technology
From: drcuthbert
Sent: Tuesday, March 30, 2004 8:16 AM
To: 'Chris Wells'; EMC-PSTC Discussion Group
Subject: RE: Multi ground plane bonding -
Chris,
your stack-up is good I think it could be improved. The central PWR-GND is far
>from the top and the bottom. You will therefore have more via inductance than
placing the PWR-GND near the top or the bottom. Figure 10 pH/mil- that gives
about 1/4 nH to get from the center to the top or bottom of the board on a 62
mil board. Above 100 MHz the via impedance will dominate over the PWR-GND
impedance.
Signal layers 4, 8, and 10 are referenced to PWR. Since PWR will have an AC
potential referenced to GND, these signal layers will have the same noise on
them, referenced to GND.
I like to use GND pour, especially on top and bottom signal layers. Just make
sure all of it is tied with vias to a GND plane. Any piece larger than 1/4
inch I like to tie with two vias. If there are floating pieces after running
the fill, you can manually delete them. Stitching the GND planes together
frequency is good. And the vias along the edges are great too.
Here is an alternate stack-up:
SIG, SLOW
PWR
GND
SIG FAST
extra space
SIG FAST
GND
SIG FAST
extra space
SIG FAST
GND
SIG SLOW
The extra space between layers 4-5 and 7-8 reduce coupling. Traces on these
two layers should be routed at right angles anyway to reduce coupling. The
downside of this stack-up is that components on the top layer have the best
PWR quality while components on the bottom have lower PWR quality, due to the
extra via length. Note that all FAST SIG layers are referenced to GND.
Dave Cuthbert
Micro Technology
From: owner-emc-p...@majordomo.ieee.org
[mailto:owner-emc-p...@majordomo.ieee.org] On Behalf Of Chris Wells
Sent: Tuesday, March 30, 2004 5:49 AM
To: EMC-PSTC Discussion Group
Subject: Multi ground plane bonding -
I have a 10 layer board with a stack up similar to that of Henry Otts articles
http://www.hottconsultants.com/techtips/pcb-stack-up-1.html
http://www.hottconsultants.com/techtips/pcb-stack-up-5.html
The stack up is
________________Signal (low-speed signals)
________________Gnd.
________________Signal (high-speed signals & clocks)
________________Signal (high-speed signals & clocks)
________________Pwr.
________________Gnd.
________________Signal (high-speed signals & clocks)
________________Signal (high-speed signals & clocks)
________________Gnd. or Pwr.
________________Signal (low-speed signals)
My Question is how does one treat the multiple GND planes?
When a part has a return do you push a via and connect all three planes
together?
I could have signals from the chip that are associated with all three planes
and I need to joing them togeter so that is my idea.
Also what to do with Ground pours top and bottom.
I have them and they are stitched to the inner planes with vias along the edge
of the board.
All ground layers are joined by the vias.
The idea is to create a low impedance high frequency wrapper around the board
and block slot antenna formation at the edge of the board.
Note I have been following the unified ground plane approach for this design.
http://www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf
AVDD power section filtered from VDD by CLC filter......
Thanks
Chris Wells
