Scott, I don't have complete answers for you; but I do have some tidbits.
With regard to layer to layer spacing of hazardous (Primary Power) traces: Rich Hughes has already replied, correctly, that this is a case of distance through insulation, not creepage or clearance, which is through air. EN 60950 has some specific requirements for distances through insulation. I agree with Mr. Hughes in that you'll probably need the standard, or the help of your test lab to make sure your distances are OK. I can relate to you a recent experience that I had with such a design. In our case, the minimum distance through insulation was 0.016", as specified by the standard (EN 61010-1); however, we were able to use a smaller layer to layer distance in our design. The reasoning goes like this: the layer to layer distance assumes that pinholes could be present in the insulation. They could be inherent, or they could be formed by stressing the insulation with high potentials. In the latter case, subsequent corona/arc discharges within a partial pinhole could develop into a full pinhole over time. If you want to use a distance smaller than the specified distance, you can sometimes do so, as long as you use multiple layers of insulation. For instance, you may be able to get away with 0.010" layer to layer spacing as long as you explicitly specify that the PCB uses three layers of FR4 to make the 0.010" gap. For instance, you could use a three layer sandwich of 0.002", 0.004" and 0.004" to provide the 0.010" gap. This MAY be acceptable because of the following reasons: The dielectric strength of 0.001" of FR4 is usually sufficient to withstand your required hipot voltage. The problem here is the possibility of the aforementioned "pinholes". However, if you use three layers of FR4, then the probability that pinholes in all three layers would line up to make a complete pinhole through the insulation is extremely small. I provide this information with the following caveats. 1. Consult the standard for yourself and/or get some cooperative design effort from your chosen safety lab before you commit the design to PCBs. (I did both) 2. The distances (0.010") and materials (FR4) that I mentioned are just examples. You'll have to customize your own design based upon the distances you need and materials that you're using. Distances may be different, depending upon the standard that you're using and the dielectric strength of the material that you select. With regard to power factor. You can either design or buy a front end to put in front of this linear regulator, which will bring its harmonics within spec. Vicor sells such modules. There are other vendors as well. If you want to design your own, you'll need to consult some design books, such as "Power Electronics" by Mohan, Undeland and Robbins. Hope this helps. Chris Maxwell Design Engineer Nettest From: [email protected] [mailto:[email protected]] On Behalf Of Scott Douglas Sent: Friday, April 09, 2004 9:20 PM To: Emc-Pstc Subject: Primary Power On PCB's I have two questions for the list today. First, product is ITE tested to EN 60950. Primary power (115 VAC) is fed to a printed circuit board. I know there are creepage and clearance requirements for the etches carrying AC that run on the surface of the board, or on any layer for that matter. That is there are spacings required between AC etches and other etches whether signal or ground or whatever. What I cannot recall is if creepage and clearance applies to etches on different layers. Say AC on etch on surface and signal on etch on first inner layer. Assume standard multilayer board with typical thicknesses. Don't recall 60950 saying anything about that and don't have a copy of the standard to review. Does creepage and clearance apply to this situation? Does the high insulation value of the FR-4 play any part in reducing the requirements? Second question is about a linear power supply with a very large toroid transformer (600+ VA) and two very large (call them garbage can sized) caps. This power supply fails Harmonics when tested to EN 61000-3-2; it is almost double the limit for harmonics currents. Short of going to a switcher, are there any solutions that are not extreme to make the supply pass the test? As always, looking forward to the diverse suggestion I am sure to read. And thanks for your input. Scott Douglas This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ieee-pses.org/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
