Thanks Ken and John, Regarding what Ken said about using a resistor and monitoring power quality. I wonder... what level of immunity testing would lead a reduction of power quality? On the surface, immunity testing to very high levels should be rather trivial. :-)
To the rest of this August forum :-) These days the wall warts can be based a SMPS design and usually my take on these are that their compact size makes capacitive coupling a possible threat to their wards. Can anybody shed some light about EFT and surge immunity testing on these kind of products (wall warts) by themselves and together with their wards? Thanks in advance. Tim Foo Ken Javor <[email protected]> 27/10/2004 11:06 AM > It seems to me that if a manufacturer of such a wall wart wanted to immunity > qualify his unit alone it would be a worst case to put a resistive load on > it and monitor output power quality not to change during application of > transient (or not exceed some TBD limit). This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Ron Pickard: [email protected] Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
