Eric,

I am not sure about your question. To pass the Hygroscopic dust test in
the past, I have not had issues if the following two items are
addressed:

1. Air is properly filtered.
2. The maximum voltage gradient between pins does not exceed 12V/mil.
(mil = thousandth of an inch)

That does not mean that a higher voltage gradient will necessarily fail
just that this level is low risk. The level was arrived at
experimentally - not with any simulations.

I have only had experience with regular FR-4 (& there high-speed
variants) and with ceramic hybrids but I cannot see that any other
laminates will have issues.

Cheers,
Marko


From: [email protected] [mailto:[email protected]] On Behalf Of Meunier,
Eric
Sent: Wednesday, December 07, 2005 1:34 PM
To: ieee pstc list
Subject: Design for GR-63 Hygroscopic Test

Hi,

Would someone know what value of surface resistivity we should assume
for
PCB design and simulation purposes in order to pass the NEBS GR-63-CORE
Hygroscopic Dust Test of Section 5.5.3 ?

Thanks,
Eric


===================================

Eric Meunier
Designer EMC/Environmental


E-mail: [email protected]

Kontron Canada Inc.
616, rue Cure-Boivin
Boisbriand, Quebec
Canada, J7G 2A7

Tel: 1-450-437-4661 ext. 2419
Fax: 1-450-437-8053

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