At 4/9/2008, MACY wrote:
What is a reasonable, not necessarily safety related, value for high voltage creep distance on FR4 PCB? I've got 2 KV on a board and need to make certain that tracks don't develop. Or, breakdown occur. I've been given a distance of 6 mm for 2 KV, but thought best to check with expertise here first. Hi Robert: You don't mention whether this is 2000 VRMS sine wave, DC, or peak. For a 2000 VRMS sine wave (2828 volts peak), the theoretical worst-case breakdown spacing through air is about 3 mm. I would be uneasy using only a 2:1 factor for spacing on the surface of an FR4 board. Maybe some others who have more experience with high voltage design will be able to provide better guidance. If you have the opportunity to use inner layers of the board, you will get much better insulation for a given spacing, and the barrier will be less susceptible to surface contamination. Joe Randolph Telecom Design Consultant Randolph Telecom, Inc. 781-721-2848 (USA) [email protected] http://www.randolph-telecom.com <http://www.randolph-telecom.com/> - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] Mike Cantwell [email protected] For policy questions, send mail to: Jim Bacher: [email protected] David Heald: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
