Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that you 
mention, do have response to GHz noise even 1 MHz unity gain opamps! Low 
frequency op amps can  generate a DC offset on their inputs from GHz digital 
noise or radio signals, a common problem for the last  45 years since I first 
observed it. Power supply rejection of op amps goes to pot pretty quickly with 
frequency as well. High frequency effects therefore are important even to low 
speed analog circuits. In some ways, one must lay out the low frequency analog 
circuit using microwave techniques to keep RF noise at bay. The circuit 
features must be keep really small,, including the bypass capacitors being kept 
extremely close (< 100 mils) to the op amp.

45 years ago, faced with opamp problems from RF noise I developed some 
techniques for keeping the op amps happy. I discuss these in my upcoming course.

Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
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Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
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On Sun, 8 Apr 2018 12:30:10 -0400, Istvan Novak  wrote:

Ken,

Again, there is no generic answer, it depends on the circuit you feed.  
Generic low speed logic can be fairly tolerant to noise, but today's 
high-speed digital chips also have a lot of analog-like circuits: PLL, 
oscillators, SerDes drivers and receivers.  Dependent on their 
construction, their tolerance to noise can be very different.  If we are 
lucky, we get that requirement from the device's data sheet, so that we 
can decide about acceptable limits rail by rail and device by device.

Dips usually dont kill a device, it may cause 'only' functional errors.  
A spike can cause damage to the chips, but only if it appears on the 
semiconductor itself.  But we do not have direct access to the 
semiconductor to measure the voltage, and as opposed to signal 
integrity, where we can deembed the package and can reliably infer the 
waveform on the silicon from a waveform measured at the pin and from a 
package model, we almost never have a model for the power path of the 
package to do the same deembedding with power noise.

Regards,
Istvan Novak



Ken Javor wrote:
> Re: [PSES] Power Integrity Question Then let’s slightly rephrase the 
> question. What sort of ripple causes problems? Is it dips - how much? 
> Spikes – again, how much?  Let’s confine this to digital logic. Analog 
> is easier because there is defined power supply ripple rejection for 
> parts plus the noise sources aren’t high speed.
>
> Ken Javor
> Phone: (256) 650-5261
>
>
> ------------------------------------------------------------------------
> *From: *John Woodgate 
> *Date: *Sun, 8 Apr 2018 08:09:47 +0100
> *To: *Ken Javor , 
> 
> *Subject: *Re: [PSES] Power Integrity Question
>
>
>
> A specific target would typically be 'less than 1/3 of the value known 
> to just provoke trouble'.
>
>
> John Woodgate OOO-Own Opinions Only
> J M Woodgate and Associates www.woodjohn.uk  
> 
> Rayleigh, Essex UK
>
> On 2018-04-08 04:25, Ken Javor wrote:
>
>
>     Re: [PSES] Power Integrity Question If the answer to how much
>     ripple is too much, or how little ripple is good enough is in all
>     cases, “it depends,” then does that mean that the pursuit of power
>     integrity has a purely functional pass/fail criteria; i.e., that
>     the unit operates properly, as opposed to a specific target on
>     ripple level?
>
>      Ken Javor
>      Phone: (256) 650-5261
>
>
>
>
>     ------------------------------------------------------------------------
>     *From: *John Woodgate  
>     
>     *Date: *Sat, 7 Apr 2018 17:58:36 +0100
>     *To: *Ken Javor 
>     
>      ,
>      
>     
>     *Subject: *Re: [PSES] Power Integrity Question
>
>
>
>     I don't think that there is a general rule that doesn't have so
>     many exceptions as to be useless. Even a 'simple' audio power
>     amplifier can show this. A conventional linear amplifier can have
>     very good PSRR (power supply rejection ratio) but a Class D
>     amplifier has zero dB PSRR - none at all.
>
>
>      John Woodgate OOO-Own Opinions Only
>      J M Woodgate and Associates www.woodjohn.uk
>      
>      
>      Rayleigh, Essex UK
>
>      On 2018-04-07 17:41, Ken Javor wrote:
>
>
>
>         Power Integrity Question There are many learned
>         books/papers/discussions on how to achieve proper power
>         integrity by way of proper PCB layout and proper capacitor
>         decoupling techniques, but what is the goal?  I don't mean the
>         functional goal, which is obvious, but rather what is the
>         metric?  Is it ripple voltage peak-to-peak, maximum excursion,
>         minimum excursion, some rms value, or...?
>
>           This question is decoupled from achieving PI for the purpose
>         of controlling radiated emissions: just asking how close to
>         pure unadulterated dc a dc rail must be in order to be
>         considered properly functional.
>
>           Understand the answer will be different for an analog rail
>         vs. a digital one, and for different digital rails, but
>         appreciate insight into what constitutes acceptable power
>         quality for all dc rails used in a typical piece of electronics.
>
>           Thank you,
>
>           Ken Javor
>           Phone: (256) 650-5261
>
>
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