Peter C. Wallace wrote:

>
>In other words the host filling the FIFOs knows exactly how many 
>(whole+fractional) steps are output each frame.
>
>  
>
OK, I guess I'm not clear on what is between the CPU and the DDS.  If 
the computer
was just placing a new value in the addend register of the DDS, then it 
would have to
know the frequency of the DDS' master oscillator to extreme precision.  
Now, maybe your
FIFO is being emptied at a rate created from the same clock, and that's 
the secret to how
it works.  The CPU just has to fill FIFO entries, knowing they will be 
pulled from the
FIFO at precise intervals.  And, if the FIFO ever runs empty, the system 
stops.  My understanding
of Window's "real-time" performance is that there is NO upper bound on 
latency to a
user-mode process.  My experience using Windows systems certainly 
confirms this
does happen.  Just pop in a CD, and there can be ** 15 second ** delays 
where the mouse
cursor doesn't move, etc.

>This was mainly done for people using Windows so that real time reponse was 
>not required to get a perfectly timed output stream.
>
>I'm working on an alternate step gen for EMC that will be free running and 
>unbuffered. Its a little more involved because you cant avoid the direction 
>setup time problem as easily as the buffered approach and therefore requires a 
>dir change deadtime step accumulater-deccumulator. I should have something 
>tommorow or Monday.
>  
>
I had to go through all the same on my stepper controller.  It isn't all 
that hard.  Especially
because direction reversals are always going to happen at low speeds, so 
a 20 us delay
of the first step in the new direction is not likely to make a motor 
lose sync.

Jon

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