Matthew Glenn Shaver wrote: (I see that while I was writing this tome, Matt clarified some things. But its already written, and it goes into more detail, so I'm posting it anyway.)
> On Sat, 2007-03-17 at 00:58 +0000, paul_c wrote: > >> On Friday 16 March 2007 18:44, Matthew Glenn Shaver wrote: >>>> src/hal/drivers/pluto_servo_firmware/pluto_servo.qsf >>> GPL - Header at the top of the file. >> Well, I guess the Altera lawyers could have a field day with that... >> CVS history says one thing for the original commit, six months later, >> something else. > > OK, that I didn't know. The original copyright header says: > > # Copyright (C) 1991-2006 Altera Corporation > # Your use of Altera Corporation's design tools, logic functions > # and other software and tools, and its AMPP partner logic > # functions, and any output files any of the foregoing > # (including device programming or simulation files), and any > # associated documentation or information are expressly subject > # to the terms and conditions of the Altera Program License > # Subscription Agreement, Altera MegaCore Function License > # Agreement, or other applicable license agreement, including, > # without limitation, that your use is for the sole purpose of > # programming logic devices manufactured by Altera and sold by > # Altera or its authorized distributors. Please refer to the > # applicable agreement for further details. > > The two referenced agreements (which I found after almost an hour of > searching Altera's website) are: > https://www.altera.com/support/software/download/license/lic-weprog_lic.html > and > http://www.altera.com/common/legal/leg-megacore_lic.html > > It's the second one of these documents that really pertains. Actually, its not. The second document relates to licensing "Megacores" from Altera. Megacores are large, pre-designed blocks. Things like CPU cores, SDRAM controllers, FFT processors, etc. Altera's own pages about Megacores are here: http://www.altera.com/products/ip/altera/mega.html http://www.altera.com/products/ip/ipm-index.html Megacores are Intellectual Property, completely independent from the tool-chain. The design tools are the equivalent of a compiler, and Megacores are equivalent to a proprietary library. If Jeff had used such a core, then of course the second license would apply. But he didn't, so it doesn't. Note that the header said "subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement" Note the OR. They are listing multiple licenses that may or may not be applicable. There are also 3rd party "megacore" type IP blocks that would have their own 3rd party licenses. But Jeff didn't use any of those either. The only Altera stuff Jeff used was the toolchain that turned his verilog files into a bitstream for programming the FPGA. Therefore the only license that is applicable is the design software (toolchain) license. As Matt found, that license is here: https://www.altera.com/support/software/download/license/lic-weprog_lic.html Interested people should feel free to read it themselves. The only restrictions it applies to the output of the toolchain are: 1) the bitstreams can only be used to program Altera devices. 2) the simulation model output may only be used for simulation. We meet both of those requirements: 1) We produce bit files for the explicit purpose of programming the Altera FPGAs on Pluto boards. 2) We don't produce simulation model output at all (I think, Jeff can confirm this), and if we do, it is used for simulation only. Altera does NOT claim any ownership of the output files. To do so would be commercial suicide, since their customers expect to retain all rights to their designs. Matt quoted a lot of nasty and restrictive language in his email, but all of it came from the Megacore License. That situation is completely different. When a person or company generates their own Verilog source code and runs it through the toolchain, they own the output, subject to the two restrictions listed above. But if a person (or more likely a company) licenses a core from someone, then the original author of the core retains rights to that core. The finished design is a combination of the core author's property and the system designer's property. That situation results in complex copyright and intellectual property issues, which is why the megacore license is about ten times as long as the design tool license. Fortunately we don't (and won't) use cores. By the way, there ARE open source cores out there. One project that is doing lots of work in that area is http://www.opencores.org/ Its encouraging that Altera is listed as a sponsor of OpenCores.org Altera is a chip maker, and they know that any logic designs, including open source ones, are an opportunity to sell more chips. Their license does not permit them to "come after" us, and in fact they benefit from Jeff's work, because they sell the chips that his firmware runs on. Finally, lets talk about the copyright statement that was in src/hal/drivers/pluto_servo_firmware/pluto_servo.qsf. That file is a "Quartus Settings File" (.qsf). It contains a bunch of directives that tell the design tools what pins the various signals should go on, and other hints and constraints that are used to guide the tools as they process the Verilog source code. The copyright was inserted in the file by the Altera GUI based qsf file editor which Jeff used at some point in the project. However, the content of the file is based on Jeff's input to the editor. It is debatable whether Altera can claim copyright on that content. In any case, it is quite possible to create the qsf file manually, and in fact Altera provides a very detailed (900+ pages) manual that lists every possible entry, to allow you to do just that: http://www.altera.com/literature/manual/mnl_qsf_reference.pdf As a worst case plan, Jeff could consult that manual and re-create a .qsf file manually, and apply any copyright he damn well pleases to it. It is nothing more than another input file for the toolchain. The situation for the Xilinx firmware for the Mesa card is very similar. The toolchain license does not prevent us from distributing either the source or the firmware, we use no proprietary cores or other IP, and all source files (including constraints files) are free of Xilinx copyrights. (Note: Xilinx also has a constraints file editor, but it does not put copyright notices in the resulting files. In any case, all of my FPGA work has used a manually generated constraints file, based only loosely on the one I got from Peter Wallace.) In short, there are no copyright violations, there will be no Altera lawyers knocking on our doors, and there will be no cease-and-desist letters. Any suggestions otherwise are misinformed (or intentional misinformation). Regards, John Kasunich ------------------------------------------------------------------------- Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT & business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
