Peter C. Wallace wrote: > <rant> > Oh it absolutely makes more sense, half the logic in our hardware step > generator is timers for holding up the rate generator to meet step/dir specs. > Yup, we have the same junk in ours! Not a huge amount of logic, actually, but a lot of complexity to be sure it manages every possible timing situation without losing a step or delaying a step when not actually required. You want it to only delay a step right near zero speed immediately after a reversal. > With quadrature all that waste logic could go away. Also with quadrature a > software step generator need only do one port write per base thread. For > buffered hardware step generators (not an EMC thing) the step generator is > much simpler bacuse it does exactly what its told. > > How much easier stepconf would be for newwbees with no step timing specs to > worry about! If I ruled the world step/dir would be banned... > </rant> > Yup, the logic all makes more sense, but step/dir is too ingrained in chips and drives.
Jon ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
