Hello List, I have run into a problem with my new revision of my pcb which adapts a 7i43 and a 7i33 to a machine of mine.
Before I had W3 in the up position, which enabled the pull ups on the 7i43. Then I inverted the polarity of the outputs in the hal layer,i.e. the output signals where active low. While designing the new pcb I thought I'd get rid of the inversion of the polarity in the hal layer and designed the output signals to be active high. Turns out that this was a *bad* idea. Now I running into the same problem as Malte on the 11th of this month in "[Emc-users] Mesa 7i43 hostmot and EMC2 exit"i,i.e. once emc2 unloads the watchdogs bite, all output are reconfigured as input. The internal pullup drive the pin high and all my outputs on the pcb are enabled. Now I was looking for a quick fix and found lines like these in the 7i43.ucf. These are the pins that I use for outputs. Pin numbers are 24 to 31 in the hal layer. 7i43u.ucf:NET "IOBITS<27>" LOC = "p27" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ; I am hoping that putting PULLDOWN here instead of PULLUP would solve my problems. Could somebody comment on that ? As anybody tried ? Could somebody synthesise a new firmware for me with these pins having internal pulldown instead of pullups. Thanks BR Max. ------------------------------------------------------------------------------ Get a FREE DOWNLOAD! and learn more about uberSVN rich system, user administration capabilities and model configuration. Take the hassle out of deploying and managing Subversion and the tools developers use with it. http://p.sf.net/sfu/wandisco-d2d-2 _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
