> Four stepgens and one pwmgen are invoked in a LinuxCNC 2.5.2 environment as
> follows, resulting in step rate limitation on all four joints: > > > > loadrt hm2_pci config="firmware=hm2/5i23/SVST4_8.BIT num_encoders=0 > num_pwmgens=1 num_3pwmgens=0 num_stepgens=4" > > > > Under this configuration, maximum step rate is limited to approximately > 250Hz, while without 5i23 pwmgen invocation the 4 stepgens perform as > expected (with good step rate headroom). > What symptom do you have? For example, irrespective of alternate commands G1 x50 Fr / G1 x0 Fr, where 100 <= r <= 2500, the joint accelerates smoothly to a maximum feedrate somewhere in the range of 170 - to be more precise, the reported step pulse interval of ~4ms (~250Hz), and eventually decelerates to the required end position. Varying steplen and stepspace have no effect (within reasonable bounds, of course - the pulse width is observed to reflect ini parameter value). The cap on joint step rate accordingly manifests in large to very large following errors, depending on the value of 's' - you will see that min_ferror is set to 50! Do you have the per axis Stepgen maxaccel set to 1.25 times the the per axis machine acceleration limits? As the attached ini file shows, stepgen_maxaccel is generally set to 4/3 of maxaccel (ratio lower in case of Z axis), but setting these to a 5/4 ratio has no impact. If this is not done you may get following errors > Having confirmed that this limitation is independent of host motherboard but > identical on two Mesa 5i23 adapters tested, and independent of pwmgen > frequency between 400Hz and 20kHz, it is expected that this is a firmware > rather than performance constraint of the FPGA on the 5i23 adapter. The ini > file is unchanged between configs with or without 5i23 pwmgen. > I doubt that this is any kind of FPGA performance constraint (the 5I23 stepgens are capable of 12 MHZ step rates) And while stepgens mixed with PWMgens is not terribly common, its used in a lot of step/dir systems with analog controlled spindles. This is exactly the application of the pwmgen, to avoid s/w pwmgen dither / speed resolution limitation. Since I agree that FPGA performance cannot be the issue here, I will pursue the recommendation of Andy Pugh to trace driver parameters - after checking the docs for raw mode invocation!
pwm-test.ini
Description: Binary data
pwm-test.hal
Description: Binary data
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