On Thu, 22 May 2014, JHC wrote:

> Date: Thu, 22 May 2014 13:56:40 +0100
> From: JHC <gd-syst...@ntlworld.com>
> Reply-To: "Enhanced Machine Controller (EMC)"
>     <emc-users@lists.sourceforge.net>
> To: emc-users@lists.sourceforge.net
> Subject: [Emc-users] Different PWM frequencies re HostMot2 pwmgen on 5i20
> 
> Hi all,
>
> Im setting up a machine with a Mesa 5i20 driving 3 DC servos via
> homemade PWM/DIR amps.
> I've got a couple of very nice ServoDisc DC servos (0-3000rpm within 60
> degrees of rotation!). I also want to get another I've seen with a 120:1
> harmonic drive for a future rotational axis.
>
> Question is this:
>
> To cut down on the ridiculous size of the output inductors I'll need for
> the ServoDisc amps Id like to use at least 40khz PWM, but I've also got
> an ESA 6F2 (3000rpm 120V 3.5Nm @9A - 17.5Nm @45A) which Id like to drive
> using 2 of 3 half bridges from an integrated gatedriver IGBT module
> which only goes up to 20khz PWM.
> Can I have 40khz or more on 1 or 2 pwmgens and 20khz on another 2?
>
> I know bugger all about FPGAs, VHDL etc so making a custom firmware isnt
> an option, just learning Linux and moving from TTL and PICs to power
> electronics has opened up a big enough can of whoop ass on me for now.
>
> JHC


Its possible but not straighforward...

All HostMot2 PWM channels share a common reference counter.
The reference counter count rate is set by the PWM frequency parameter for all 
PWM generators. However each individual PWM generator has a resolution setting
that allows selection of 9,10,11, or 12 bit PWM resolution.

So for example you could set the PWM frequency to 20 KHz (the driver will then
select 12 bit resolution for all PWM generators since it selects the best 
resolution it can achieve at the chosen PWM rate and 12 bits is possible at 
20 KHz and the 5I20s 100 MHz clock-high rate)

You could than use the raw-write facility in the driver to overwrite the
PWM mode register for the 40 KHz channels to select 11 bit resolution instead.
This will double the output frequency (you could use up to 8X (160 KHz)
if needed by chosing 9 bits resolution)

Once this is done you would have to restrict the PWM setting of the high 
frequency channels in HAL to 1/2 their normal range or the PWM woud "wrap" 
since the driver doesn't know that the PWM resolution has changed. This can be 
done by setting the PID comps max output parameter.

Here is the (per channel) register that needs to be changed: (from the regmap 
file)

PWM mode registers 6 bits

Bit 1,0 = width select  (With FPGA compile time constant PWM width = 13)
00 = 9 bit PWM
01 = 10 bit PWM
10 = 11 bit PWM
11 = 12 bit PWM

Bit 2 = PWM mode select
0 = Straight (Sawtooth) PWM 
1 = Symmetrical (Triangle) PWM

Bit 4,3 = PWM output mode select
00 = Normal Sign Magnitude PWM&DIR outputs normal
01 = Normal Sign Magnitude PWM&DIR outputs swapped (for locked antiphase)
10 = Up/down mode
11 = PDM mode (12 bits)

Bit 5 = Double Buffered mode
When bit 5 is set, the PWMval register is not updated until the beginning of a 
PWM cycle, avoiding extra transitions in the output PWM waveform. This adds 
an extra delay of 0 to PWMWidth/PWMClock (normal mode) or PWMWidth*2/PWMClock
(Symmetrical mode) between when the host writes the PWMVal register and the 
PWM output is updated. This mode should be used with HBridges.

These registers are at 0x410X in the FPGA memory space (X= 0,4,8, etc for PWM 
0,1,2 etc)
so to set the PWM resolution to 11, you would write 0x00000022 to 0x410X (11 
bit resolution and buffered mode)

This can be done with raw-write in hal:

setp  hm2_5i20.0.raw.write_address 0x4100
setp  hm2_5i20.0.raw.write_data 0x00000022
setp  hm2_5i20.0.raw.write_strobe true

  (and duplicated for the other channels that need 2x PWM rates)



>
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Peter Wallace
Mesa Electronics

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