Jeff

Excellent answer - now I not only know, but also understand.  The fact that the 
documentation wasn't all updated is real-life ;-).  Anyone expecting otherwise 
hasn't attempted a project 1/1000th of the size of LinuxCNC. 

I'll try to do my "tuppence-worth" of contribution, and feed any 
inconsistencies I find through to John Thornton.

Cecil

-----Original Message-----
From: Jeff Epler [mailto:[email protected]] 
Sent: 02 July 2014 02:45 PM
To: Enhanced Machine Controller (EMC)
Subject: Re: [Emc-users] Float precision/size?

On Wed, Jul 02, 2014 at 11:50:23AM +0000, Churms, Cecil wrote:
> On page 4 of the HAL Manual V2.6.0-pre4, 2014-06-12 a float is defined as 64 
> bits (i.e which I refer to as a double in my programming), which I take to be 
> the case within a HAL context.
> 
> However, on page 44 of the same Manual, it is defined as 32 bits (i.e 
> typically a float).
> 
> Which is correct?  Or am I missing something.

Originally, linuxcnc used 32-bit (C "float"s) for HAL items of type float.  
This led to problems in real-world systems---for example, given a 2048 
cycles-per-revolution encoder running at 1000 RPM, in well under an hour the 
precision of a 32-bit float is no longer enough to represent each count on the 
encoder as a distinct floating-point value, so there is a real need for a 
higher precision value than C "float".

This original decision was made conservatively, because it was not known 
whether 64-bit floats could be stored atomcally on then-current CPU 
architectures.

The basic atomicity guarantee of hal types are that, when reading one value at 
the same time as someone else is writing a value, you see either the old value 
or the new value.  In particular, you can't see a value that is a mix of bytes 
from the old value and the new value.

In 2008, I read some Intel Pentium and AMD Athlon CPU manuals, and saw that the 
necessary guarantee is made for "double"-precision numbers that are stored at 
8-bit aligned locations.  I wish that I had recorded what these references 
were, but all I have is my series of empirical blog posts from 2008:
http://emergent.unpythonic.net/01189609097
http://emergent.unpythonic.net/01225549319
http://emergent.unpythonic.net/01225680565

After a bit of scrounging, here's an Intel reference, from "IA-32 Intel(R) 
Architecture Software Developer’s Manual Volume 3: System Programming Guide"
(2001), section 7.1.1 Guaranteed Atomic Operations:

    The Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors
    guarantee that the following basic memory operations will always be carried
    out atomically:
        * Reading or writing a byte.
        * Reading or writing a word aligned on a 16-bit boundary.
        * Reading or writing a doubleword aligned on a 32-bit boundary.

    The Pentium 4, Intel Xeon, and P6 family processors guarantee that the
    following additional memory operations will always be carried out
    atomically:
        * Reading or writing a quadword aligned on a 64-bit boundary. (This
          operation is also guaranteed on the Pentium processor.)

In the end, we did change from floats to doubles for linuxcnc 2.5.0, and some 
of the documentation simply wasn't updated.

Jeff

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