> >>> ... > >>> Modern disclaimer: I have no clue what sort of priority is given DMA by > >>> todays crop of CPU's. Sure they've gotten faster, but are they better? > >> > >> It's a bit off-topic, but anyways: DMA controllers in recent > >> microcontrollers can be quite complex beasts, far from a simple > >> incrementing pointer for copy operations. Some use dynamic descriptors > >> in memory, which hold the DMA configuration. One of the config options > >> in each descriptor holds the address of the next descriptor. With this, > >> you can generate "any number" of such descriptors and then start the DMA > >> with the address of the first and it will (optionally looping forever) > >> copy N words from here to there, then M words from foo to bar, followed > >> by K words, etc. without any CPU intervention at all. Usually it is also > >> possible to trigger the DMA using a hardware timer, so you could get > >> away without any interrupt for this transfers at all. But of course the > >> DMA controller has to access the bus as well, so if the CPU is doing > >> some heavy memory access on its own, the DMA may be slowed down quite much. > > > > Are you sure CPU slow down DMA and not the opposite? > > Depends on the priorities, the DMA may be configurable to get higher > priority than the CPU. But I'd suspect the "CPU comes first" approach to > be more common, as the CPU should usually be busy with not so memory > intensive tasks, so performance will increase if it only has to take the > bus every once in a while and continue immediately with its work, while > the DMA is using all the rest of the bandwidth. > > Bye, > Philipp
Ideally DMA priority should depend on how often transfers are done and scheduling priorities assigned according rate monotonic since a clock cycle blocked by memory bus busy essential use that clock cycle. ADC may be around 1MHz altough only one read/write each time so this should certainly have higher priority than any CPU task. If DMA is used for Ethernet packets and they are transferred at 1kHz while there are a faster servo loop it should however have lower priority than servo loop. I read somewhere about graphic cards on ordinary computers doing huge DMA transfers blocking CPU and they should certainly have lower priority than faster real time tasks. I would however guess it is possible to speed up memory accesses if they are done sequentially and ordinary computers are known to maximize throughput. This is the ideal situation then the hardware of course have limititions. Nicklas Karlsson ------------------------------------------------------------------------------ Transform Data into Opportunity. Accelerate data analysis in your applications with Intel Data Analytics Acceleration Library. Click to learn more. http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140 _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
