Hi all, Too happy too soon. That is what happens.
There seems to be one additional problem when configuring the SPI port. After a restart of the Pi everything went to bad again. After some digging I noticed that there might be a data-barrier problem, where peripheral register access can become out-of-order. The ARM has the __sync_synchronize() (via gcc) to insert DMB (data-memory-barrier) instructions when you need to guarantee ordering. Inserting DMB made things worse, such that sometimes the setup is 32MHz and sometimes 50MHz. Well, actually, it exposes a deeper problem. This is a Pi3, a 4-core SMP machine. DMBs and peripheral setup probably requires that no other cores are crossing peripherals while doing setup (or the process/thread is rescheduled onto a different core). For the Pi3 you probably need to lock this specific setup operation to one core and one core only. I noticed at startup that several interesting things happen, and I assume that a lot of processes and threads are spawned while doing startup. That also means that all bets are off in this sensitive time period and could explain why SPI keeps hopping between different setup states. Anybody care to comment or suggest a way to lock that part of the code to a core? -- Greetings Bertho (disclaimers are disclaimed) ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
