On Mon, Nov 05, 2012 at 10:17:34PM -0300, Paulo Alcantara wrote: > On Mon, Nov 5, 2012 at 10:07 PM, Jim Kukunas > <james.t.kuku...@linux.intel.com> wrote: > > > > On Tue, Nov 06, 2012 at 01:41:01AM +0100, Vincent Torri wrote: > > > On Tue, Nov 6, 2012 at 1:32 AM, Paulo Alcantara <pca...@profusion.mobi> > > > wrote: > > > > On Mon, Nov 5, 2012 at 7:12 PM, Sebastian Dransfeld > > > > <s...@tango.flipp.net> wrote: > > > >> Program received signal SIGILL, Illegal instruction. > > > >> 0x00491f8b in _mm_lddqu_si128 (__P=0xbfffb5b0) at > > > >> /usr/lib/gcc/i686-linux-gnu/4.6/include/pmmintrin.h:111 > > > >> 111 return (__m128i) __builtin_ia32_lddqu ((char const *)__P); > > > >> (gdb) bt > > > >> #0 0x00491f8b in _mm_lddqu_si128 (__P=0xbfffb5b0) at > > > >> /usr/lib/gcc/i686-linux-gnu/4.6/include/pmmintrin.h:111 > > > >> #1 _op_blend_pas_dp_sse3 (s=0xbfffb5b0, m=0x0, c=0, d=0xbfffb6b0, > > > >> l=64) > > > >> at lib/evas/common/evas_op_blend/op_blend_pixel_sse3.c:59 > > > >> #2 0x004b0d34 in evas_common_op_sse3_test () at > > > >> lib/evas/common/evas_op_blend/op_blend_master_sse3.c:73 > > > >> #3 0x00465867 in evas_common_cpu_sse3_test () at > > > >> lib/evas/common/evas_cpu.c:72 > > > >> #4 0x00465983 in evas_common_cpu_feature_test (feature=0x465850 > > > >> <evas_common_cpu_sse3_test>) > > > >> at lib/evas/common/evas_cpu.c:138 > > > >> #5 0x00465ad3 in evas_common_cpu_init () at > > > >> lib/evas/common/evas_cpu.c:183 > > > >> > > > >> pentium-m > > > >> flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca > > > >> cmov clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx up bts est tm2 > > > >> > > > > > > > > Weird. Looks like SSE3 support isn't being checked properly through > > > > CPUID. > > > > > > the check in configure is not sufficient : host detection + detection > > > of a file, which exists on this pentium M. So something more should be > > > done, I guess, don't know what, though > > > > The host detection + header check is _NOT_ a check as to whether the > > processor supports SSE3, but rather whether the build environment can > > compile code with SSE3 intrinsics. > > > > The real check occurs at runtime in evas_common_cpu_feature_test(), where > > we attempt to run a function consisting of the feature in question while > > trapping for SIGILL and SIGSEGV. If we catch either signal, we disable > > support > > for the associated feature. > > > > In this case, the SIGILL is expected, however it seems the signal > > handlers were not properly setup. > > Makes sense. So I'm just wondering why not simply check for a specific > CPU feature with CPUID instead of > catching either SIGILL or SIGSEV by running the function consisting of > the feature ?
Probably to share code with architectures that lack CPUID. -- Jim Kukunas Intel Open Source Technology Center
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