The following Fedora EPEL 6 Security updates need testing:
https://admin.fedoraproject.org/updates/libmodplug-0.8.8.3-2.el6
https://admin.fedoraproject.org/updates/asterisk-1.8.4.2-1.el6.1
https://admin.fedoraproject.org/updates/chm2pdf-0.9.1-8.el6
https://admin.fedoraproject.org/updates/ejabberd-2.1.8-2.el6
https://admin.fedoraproject.org/updates/torque-2.5.5-2.el6
https://admin.fedoraproject.org/updates/erlang-R14B-02.1.el6
The following builds have been pushed to Fedora EPEL 6 updates-testing
libsigsegv-2.10-1.el6
perl-File-pushd-1.00-0.3.1.el6
python-myhdl-0.7-1.el6
Details about builds:
================================================================================
libsigsegv-2.10-1.el6 (FEDORA-EPEL-2011-3604)
Library for handling page faults in user mode
--------------------------------------------------------------------------------
Update Information:
Introducing libsigsegv to epel-6.
--------------------------------------------------------------------------------
================================================================================
perl-File-pushd-1.00-0.3.1.el6 (FEDORA-EPEL-2011-3605)
Change directory temporarily for a limited scope
--------------------------------------------------------------------------------
Update Information:
This package is shipped only on some architectures for RHEL. I was asked to add
it according to new guidelines
https://fedoraproject.org/wiki/EPEL:Packaging#Limited_Arch_Packages
into ppc and so for EPEL.
--------------------------------------------------------------------------------
================================================================================
python-myhdl-0.7-1.el6 (FEDORA-EPEL-2011-3603)
A python hardware description and verification language
--------------------------------------------------------------------------------
Update Information:
python-myhdl is a Python hardware description and verification language that
helps you go from Python to silicon. MyHDL code can be converted to Verilog and
VHDL. It can also be used to convert signals, do co-simulation with Verilog,
generating test benches with test vectors for VHDL, Verilog and supports
viewing waveform by tracing signal changes in a VCD file.
--------------------------------------------------------------------------------
References:
[ 1 ] Bug #710848 - Review Request: python-myhdl - A python hardware
description and verification language
https://bugzilla.redhat.com/show_bug.cgi?id=710848
--------------------------------------------------------------------------------
_______________________________________________
epel-devel-list mailing list
epel-devel-list@redhat.com
https://www.redhat.com/mailman/listinfo/epel-devel-list
